Lattice Programmable Chip LFXP2-5E-5TN144C 100I/O 5K LUTs Inst- On DSP 1.2V -5 Spd

Specifications

Description

LatticeXP2™ devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells

in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on,

infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory

and design security. The parts also support Live Update technology with TransFR, 128-bit AES Encryption

and Dual-boot technologies. The LatticeXP2 FPGA fabric was optimized for the new technology from the

outset with high performance and low cost in mind. LatticeXP2 devices include LUT-based logic, distributed

and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and

enhanced sysDSP blocks. Lattice Diamond® design software allows large and complex designs to be efficiently

implemented using the LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available

for popular logic synthesis tools. The Diamond software uses the synthesis tool output along with the constraints

from its floor planning tools to place and route the design in the LatticeXP2 device. The Diamond tool extracts the

timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity

Features

1.1.1. Flexible Logic Architecture

• Instant-on • Infinitely reconfigurable

• Single chip • FlashBAK™ technology

• Serial TAG memory

• Design security 1.1.2. Live Update Technology

• TransFR™ technology

• Secure updates with 128 bit AES encryption

• Dual-boot with external SPI 1.1.3. sysDSP™ Block

• Three to eight blocks for high performance Multiply and Accumulate

• 12 to 32 18x18 multipliers

• Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers

1.1.4. Embedded and Distributed Memory

• Up to 885 Kbits sysMEM™ EBR

• Up to 83 Kbits Distributed RAM 1.1.5. sysCLOCK™ PLLs

• Up to four analog PLLs per device

• Clock multiply, divide and phase shifting

1.1.6. Flexible I/O Buffer

• sysI/O™ buffer supports:

• LVCMOS 33/25/18/15/12; LVTTL

• SSTL 33/25/18 class I, II

• HSTL15 class I; HSTL18 class I, II

• PCI

• LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS

1.1.7. Pre-engineered Source Synchronous Interfaces

• DDR / DDR2 interfaces up to 200 MHz

• 7:1 LVDS interfaces support display applications

• XGMII 1.1.8. Density And Package Options

• 5k to 40k LUT4s, 86 to 540 I/O

• csBGA, TQFP, PQFP, ftBGA and fpBGA packages

• Density migration supported

1.1.9. Flexible Device Configuration

• SPI (master and slave) Boot Flash Interface

• Dual Boot Image supported

• Soft Error Detect (SED) macro embedded

1.1.10. System Level Support

• IEEE 1149.1 and IEEE 1532 Compliant

• On-chip oscillator for initialization and general use

• Devices operate with 1.2 V power supply

Trading Guide

Shenzhen Retechip® Electronic Technology Co., Ltd. was established in 2013, specializing in electronic components distribution business.The products are widely used in communication equipment, power supply, medical electronics, automotive electronics, digital electronics, industrial electronics, display modules, intelligent electronics, new energy, the Internet of things, 5G productsand other fields，With high-quality products, reasonable prices, rapid distributionand timely service, we can provide customers with the most cost-effective products and save customers a lot of time.