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Professional quality, beyond value.
3 Years
| Ask Lasest Price | |
| Brand Name : | Lattice |
| Model Number : | LCMXO256C-3TN100C |
| Price : | Please contact us |
| Payment Terms : | T/T, Western Union, PayPay, MoneyGram |
| Supply Ability : | 5000pcs Per Mouth |
| Delivery Time : | 3-5work days |
Programmable Fpga LCMXO256C-3TN100C MachXO Family 78 I/O 256 LE TQFP-100
Specifications
| Product Attribute | Attribute Value |
|---|---|
| Lattice | |
| Product Category: | FPGA - Field Programmable Gate Array |
| LCMXO256C | |
| 256 LE | |
| 78 I/O | |
| 1.71 V | |
| 3.465 V | |
| 0 C | |
| + 85 C | |
| SMD/SMT | |
| TQFP-100 | |
| Tray | |
| Brand: | Lattice |
| Distributed RAM: | 2 kbit |
| Height: | 1.4 mm |
| Length: | 14 mm |
| Maximum Operating Frequency: | 500 MHz |
| Number of Logic Array Blocks - LABs: | 32 LAB |
| Operating Supply Current: | 13 mA |
| Operating Supply Voltage: | 1.8 V/2.5 V/3.3 V |
Description
The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs
and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic.
These devices bring together the best features of CPLD and FPGA devices on a single chip
Features
• Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single chip, no external configuration memory required
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable through JTAG port
• Supports background programming of non volatile memory
• Sleep Mode
• Allows up to 100x static current reduction
• TransFR™ Reconfiguration (TFR)
• In-field logic update while system operates
• High I/O to Logic Density
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
• Lead free/RoHS compliant packaging
• Embedded and Distributed Memory
• Up to 27.6 Kbits sysMEM™ Embedded Block RAM
• Up to 7.7 Kbits distributed RAM
• Dedicated FIFO control logic
• Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL
• PCI
• LVDS, Bus-LVDS, LVPECL, RSDS
• sysCLOCK™ PLLs
• Up to two analog PLLs per device
• Clock multiply, divide, and phase shifting
• System Level Support
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator
• Devices operate with 3.3 V, 2.5 V, 1.8 V or 1.2 V power supply
• IEEE 1532 compliant in-system programmin
Trading Guide
| Shipping | Delivery period | For in-stock parts, orders are estimated to ship out in 3 days.Once
shipped, estimated delivery time depends on the below carriers you
chose: |
| Shipping rates | After confirming the order, we will evaluate the shipping cost based on the weight of the goods | |
| Shipping option | We provide DHL, FedEx, EMS, SF Express, and Registered Air Mail international shipping. | |
| Shipping tracking | We will notify you by email with tracking number once order is shipped. | |
Returning warranty | Returning | Returns are normally accepted when completed within 30 days from date of shipment.Parts should be unused and in original packaging.Customer has to take charge for the shipping. |
| Warranty | All Retechip purchases come with a 30-day money-back return policy, This warranty shall not apply to any item where defects have been caused by improper customer assembly,failure by customer to follow instructions, product modification, negligent or improper operation | |
| Ordering | Payment | T/T,PayPal, Credit Card includes Visa, Master, American Express. |
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