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Professional quality, beyond value.
3 Years
| Ask Lasest Price | |
| Brand Name : | Altera |
| Model Number : | EPM570F256C5N |
| Price : | Please contact us |
| Payment Terms : | T/T, Western Union, PayPay, MoneyGram |
| Supply Ability : | 2000pcs Per Mouth |
| Delivery Time : | 2-3work days |
Programmable Integrated Circuits EPM570F256C5N MAX II Device 160 I/O Programmable Logic IC
Specifications
| Product Attribute | Attribute Value |
|---|---|
| Product Category: | CPLD - Complex Programmable Logic Device |
| EPM570 | |
| SMD/SMT | |
| FBGA-256 | |
| 2.5 V, 3.3 V | |
| 440 | |
| 160 I/O | |
| 3.6 V | |
| 2.375 V | |
| 0 C | |
| + 70 C | |
| 304 MHz | |
| 5.4 ns | |
| Tray | |
| Memory Type: | Flash |
| Number of Logic Array Blocks - LABs: | 57 |
| Number of Logic Elements: | 570 |
| Operating Supply Current: | 55 mA |
Description
The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layer-metal-flash process,
with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile
storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other
CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system
programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable
solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control,
and device configuration control.
Features
The MAX II CPLD has the following features:
Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 25 µA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and
programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group
(PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
Trading Guide
| Shipping | Delivery period | For in-stock parts, orders are estimated to ship out in 3 days.Once
shipped, estimated delivery time depends on the below carriers you
chose: |
| Shipping rates | After confirming the order, we will evaluate the shipping cost based on the weight of the goods | |
| Shipping option | We provide DHL, FedEx, EMS, SF Express, and Registered Air Mail international shipping. | |
| Shipping tracking | We will notify you by email with tracking number once order is shipped. | |
Returning warranty | Returning | Returns are normally accepted when completed within 30 days from date of shipment.Parts should be unused and in original packaging.Customer has to take charge for the shipping. |
| Warranty | All Retechip purchases come with a 30-day money-back return policy, This warranty shall not apply to any item where defects have been caused by improper customer assembly,failure by customer to follow instructions, product modification, negligent or improper operation | |
| Ordering | Payment | T/T,PayPal, Credit Card includes Visa, Master, American Express. |
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